3D Integration (Design for Test) engineer

Responsibility:

1.Conduct research on DFT (Design for Test) methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure analysis.
2.Develop DFT testing methodologies for 3DIC chips, and conduct research on defect mechanisms, fault simulation, and failure analysis related to 3DIC and IO interconnects.
3.Explore DFT testing approaches for Memory, emerging NVM (Non-Volatile Memory), and analog IP, with research experience in memory and analog defect mechanisms, fault models, and failure analysis.
4.Responsible for system-level, end-to-end DFX (Design for Excellence) architecture and test implementation, with in-depth understanding of chip lifecycle management concepts and methodologies.

Requirenment:

1. Technical Expertise Requirements
    (1) Familiar with DFT technologies such as MBIST, SCAN, and ATPG, as well as semiconductor manufacturing processes and device structures.
    (2) Knowledge of digital and analog circuit failure mechanisms, fault modeling, and test algorithms.
    (3) Research experience in digital circuit defect mechanisms, fault simulation, and failure analysis.
    (4) Research experience in 3DIC and IO interconnect defects, fault simulation, and failure analysis.
    (5) Research experience related to memory or analog circuit defect modeling, simulation, and failure analysis.
    (6) Experience in system-level DFX implementation, protection strategies, and failure localization techniques.

2. Educational Requirements
    (1) Master’s degree or above
    (2) Majors in Electronics, Microelectronics, Communications, Automation, Semiconductor Engineering, Mathematics, Physics, Chemistry, or related fields.

3. Work Experience
5–10 years of relevant experience.